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ad v anc e d micro devices am48 6 ? dx4 3-volt processo r high-performance, clock-selectable, 3.3 v, 32-bit microprocessor distinctive characteristic s operating voltage range 3.3 v 0.3 v ? 12 0 -mhz operating frequency uses a 40-mhz external bu s ? 10 0 -mhz operating frequency uses a 33-mhz external bu s ? wide range of chipsets and support available through the amd fusionp c s m progra m high integration o n -chi p ? 8 -kbyte code and data cach e ? floating-point uni t ? paged, virtual memory managemen t hig h -performance desig n ? frequent instructions execute in one cloc k ? 105.6-million bytes/second burst bus at 33 mh z ? 128-million bytes/second burst bus at 40 mh z ? 0 . 5 -micron cmos process technolog y ? dynamic bus sizing for 8, 16, and 3 2 -bit buse s complete 3 2 -bit architectur e ? address and data buse s ? all register s ? 8, 16, and 3 2 -bit data type s multiprocessor suppor t ? multiprocessor instruction s ? cache consistency protocol s ? support for secon d -level cach e standard 16 8 -pin pga packag e supports environmental protection agency?s (epa) ?energy star? program ? energy management capability provides exce l - lent base for energy-efficient desig n ? works with a variety of energy efficient, power managed device s publication # 19160 re v : d amendmen t /0 issue date: july 1995 general descriptio n the AM486DX4 microprocessor is a high-perfo r mance 486 desktop solution that provides optimal price / perfo r - mance for high-end 486 power-managed systems. the AM486DX4 cpu offers superior local bus graphics pe r - formance for microsof t ? window s ? . using amd?s speed-multiplying technology, the AM486DX4 cpu and cache operate two to three times faster than the external memory bus. it is manufactured using amd?s new 3.3-v cmos process technology to consume about 2.6 watts of power at 100 mhz or 3.2 watts at 120 mhz. this 3.3-v technology provides s u - perior solutions for low-power epa?s energy star green pcs and portables . the AM486DX4 processor operates with a 1x clock i n - put. this 1x clock simplifies system design by redu c ing the clock frequency required by external devi c es. the 1x clock also reduces rf emission and simplifies clock generation. the input signal is doubled or tripled inte r - nally to achieve the maximum 2x or 3x operating fr e - quency. the phases of the core clock are controlled by an internal phase lock loop (pll) circuit. preliminary this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice.
amd 2 AM486DX4 microprocessor p r e l i m i n a r y block diagra m floatin g - point unit floatin g - point register file central and protection test unit control rom instruction decode barrel shifter alu register file segmentation unit descriptor registers paging unit translation lookaside buffer limit and attribute pla cache unit 8 - kbyte cache prefetcher 32-byte code queue 2 x 16 bytes address drivers bus control request sequencer write buffers 4 x 80 data bus transceivers burst bus control bus size control cache control parity generation and control linear address bus 32-bit data bus 32-bit data bus 32 32 32 24 32 20 2 32 32 32 128 micr o - instruction decoded instruction path code stream physical address pcd, pwt 32 base/ index bus displacement bus bus interface a3 1 - a2, be 3 - be0 d3 1 - d0 ad s , w / r , d / c , m / i o , pcd, pwt, rd y , loc k , ploc k , bof f , a20 m , breq, hold, hlda, reset, intr, nmi, fer r , ignn e , u p brd y , blast bs1 6 , bs8 ke n , flus h , ahold, ead s pch k , dp 3 - dp0 6 4 - bit interunit transfer bus am486 cpu pipelined 3 2 -bit microarchitectur e boundary scan control tdi, tdo tms, tc k cloc k multiplie r clk clkmul core clock powe r plane s voldet v c c , v s s 19160c-00 1
3 AM486DX4 microprocessor amd p r e l i m i n a r y ordering informatio n standard product s amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below . valid combination s valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations . valid combinations -120nv8t -100nv8 t 80486dx4 a -12 0 80486dx 4 speed option device number/description package type a -120 = 120 mhz -100 = 100 mh z 80486dx4 AM486DX4 hig h -performance, clock-selectable, 3 2 -bit microprocessor a = 16 8 -pin pga (pin grid array ) cache siz e 8 = 8 kbyte s voltag e v = 3.3 volt core, 5 v tolerant i/ o cache typ e t = write-throug h v 8 t ice microcod e blank = contains ice microcod e n = no ice microcod e n
amd 4 AM486DX4 microprocessor p r e l i m i n a r y connection diagram s AM486DX4 cpu pin side vie w 16 8 -pin pga (pin grid array) packag e ploc k n c blas t ad s up v c c v s s v s s v s s v c c v c c v c c v c c v c c v c c v c c v s s v s s v s s v s s v s s v s s v s s a27 a26 a23 voldet a14 a12 a10 a6 a4 a28 a25 a18 a15 a11 a8 a3 a31 a17 a19 a21 a24 a22 a20 a16 a13 a9 a5 a7 a2 breq pchk d0 a29 a30 hlda d2 d1 dp0 lock d4 d6 d7 pwt d14 be0 d5 d16 be2 be1 pcd d3 dp2 brdy d12 nc dp1 d8 d15 ken rdy be3 d10 hold d9 d13 d17 a20m bs8 boff d11 d18 clk d27 d26 d28 d30 nc nc nc flush ferr reset bs16 d19 d21 d25 d31 nc nc clkmul tms nmi tdo eads d20 d22 tck d23 dp3 d24 d29 nc nc nc tdi intr ahold ignne 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 s r q p n m l k j h g f e d c b a s r q p n m l k j h g f e d c b a 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 v s s v c c v s s in c v s s v c c v s s v c c v s s v c c v s s v c c v s s v c c v s s v c c v s s v c c v s s v c c v s s v c c v s s m / i o w / r d / c v c c v c c v s s v s s v s s v c c v c c v c c v s s v s s v s s 19160c-002 note : nc = no connect. to guarantee functionality with future revisions, these pins must not be connected .
5 AM486DX4 microprocessor amd p r e l i m i n a r y connection diagram s AM486DX4 cpu top side vie w 16 8 -pin pga (pin grid array) packag e note : nc = no connect. to guarantee functionality with future revisions, these pins must not be connected . n c pch k ploc k blas t ad s up v c c v s s v s s v s s v c c v c c v c c v c c v c c v c c v c c v s s v s s v s s v s s v s s v s s v s s a27 a26 a23 voldet a14 a12 a10 a6 a4 a28 a25 a18 a15 a11 a8 a3 a31 a17 a19 a21 a24 a22 a20 a16 a13 a9 a5 a7 a2 d0 a29 a30 hlda v c c v s s d2 d1 dp0 lock d4 d6 d7 pwt d14 be0 d5 d16 be2 be1 pcd d3 dp2 brdy d12 nc dp1 d8 d15 ken rdy be3 d10 hold d9 d13 d17 a20m bs8 boff d11 d18 clk d27 d26 d28 d30 nc nc nc flush ferr reset bs16 d19 d21 d25 d31 nc nc clkmul tms nmi tdo eads d20 d22 tck d23 dp3 d24 d29 nc nc nc tdi intr ahold ignne 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 s r q p n m l k j h g f e d c b a s r q p n m l k j h g f e d c b a 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 v s s v c c v s s in c v s s v c c v s s v c c v s s v c c v s s v c c v s s v c c v s s v c c v s s v c c v s s v c c v s s m / i o w / r d / c v c c v c c v s s v s s v s s v c c v c c v c c v s s v s s v s s bre q 19160c-00 3
amd 6 AM486DX4 microprocessor p r e l i m i n a r y pin designations (functional grouping ) addres s dat a contro l tes t inc/n c v c c v s s pin nam e pin no . pin nam e pin no . pin nam e pin no . pin nam e pin no . pin no . pin no . pin no . a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 q-14 r-15 s-16 q-12 s-15 q-13 r-13 q-11 s-13 r-12 s-7 q-10 s-5 r-7 q-9 q-3 r-5 q-4 q-8 q-5 q-7 s-3 q-6 r-2 s-2 s-1 r-1 p-2 p-3 q-1 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 p-1 n-2 n-1 h-2 m-3 j-2 l-2 l-3 f-2 d-1 e-3 c-1 g-3 d-2 k-3 f-3 j-3 d-3 c-2 b-1 a-1 b-2 a-2 a-4 a-6 b-6 c-7 c-6 c-8 a-8 c-9 b-8 a20m ads ahold be0 be1 be2 be3 blast boff brdy breq bs8 bs16 clk clkmul d / c dp0 dp1 dp2 dp3 eads ferr flush hlda hold ignne intr ken lock m / io nmi pcd pchk plock pwt rdy rese t up voldet w / r d-15 s-17 a-17 k-15 j-16 j-15 f-17 r-16 d-17 h-15 q-15 d-16 c-17 c-3 b-13 m-15 n-3 f-1 h-3 a-5 b-17 c-14 c-15 p-15 e-15 a-15 a-16 f-15 n-15 n-16 b-15 j-17 q-17 q-16 l-15 f-16 c-16 c-11 s-4 n-1 7 tck tdi tdo tms a-3 a-14 b-16 b-14 a-10 a-12 a-13 b-10 b-12 c-10 c-12 c-13 g-15 j-1 r-17 b-7 b-9 b-11 c-4 c-5 e-2 e-16 g-2 g-16 h-16 k-2 k-16 l-16 m-2 m-16 p-16 r-3 r-6 r-8 r-9 r-10 r-11 r-14 a-7 a-9 a-11 b-3 b-4 b-5 e-1 e-17 g-1 g-17 h-1 h-17 k-1 k-17 l-1 l-17 m-1 m-17 p-17 q-2 r-4 s-6 s-8 s-9 s-10 s-11 s-12 s-1 4 note s : inc = internal no connect (j-1). nc = no connect (a-10, a-12, a-13, b-10, b-12, c-10, c-12, c-13, g-15, r-17). voldet is connected internally to v s s .
amd AM486DX4 microprocessor 7 p r e l i m i n a r y logic symbo l dp3?dp0 a31?a 4 cl k a20 m m / i o am486 cpu w / r d / c 17852b-114 28 2 loc k 4 be 3 ? be 0 clock address bus bus cycle definition address mask ploc k bs 8 bs1 6 ad s rd y bus cycle control 32 4 int r nm i rese t interrupts pchk a3?a 2 brdy blast pwt pcd ken flush eads ahold data parity data bus burst control page cacheability invalidation cache control / d31?d0 tm s td i td o tc k ieee test access port bus arbitration bre q hol d hld a bof f up upgrade processor present clkmu l fer r ignn e numeric error reporting volde t clock multiplier
amd 8 AM486DX4 microprocessor p r e l i m i n a r y pin description s the following paragraphs define the AM486DX4 cpu pins (signals) . a31?a4/a3?a 2 address lines (inputs/outputs)/(outputs ) a31?a2, together with the byte enables be 3 ? be 0 , d e - fine the physical area of memory or input/output space accessed. address lines a31?a4 are used to drive a d - dresses into the microprocessor to perform cache line invalidations. input signals must meet setup and hold times, t 2 2 and t 2 3 . a31?a2 are not driven during bus or address hold. a20 m address bit 20 mask (active low; input ) when asserted, the AM486DX4 microprocessor masks physical address bit 20 (a20) before performing a loo k - up to the internal cache or driving a memory cycle on the bus. a20 m emulates the address wraparound at 1 mbyte, which occurs on the 8086. a20 m is active low and should be asserted only when the processor is in real mode. this pin is asynchronous but should meet setup and hold times, t 2 0 and t 2 1 , for recognition in any specific clock. for proper operation, a20 m should be sampled high at the falling edge of reset . ad s address status (active low; output ) ad s indicates that a valid bus cycle definition and a d - dress are available on the cycle definition lines and a d - dress bus. ad s is driven active in the same clock as the addresses are driven. ad s is active low and is not dri v - en during bus hold . ahol d address hold (active high; input ) this request allows another bus master access to the AM486DX4 microprocessor?s address bus for a cache invalidation cycle. the AM486DX4 microprocessor stops driving its address bus in the clock following ahold going active. only the address bus is floated during address hold; the remainder of the bus remains active. ahold is active high and is provided with a small internal pul l -down resistor. for proper operation, ahold must meet setup and hold times, t 1 8 and t 1 9 . be 3 ? be 0 byte enables (active low; outputs ) these pins indicate active bytes during read and write cycles. during the first cycle of a cache fill, the external system should assume that all byte enables are active. be 3 applies to d31?d24, be 2 applies to d23?d16 , be1 applies to d15?d8, and be 0 applies to d7?d0. be 3 ? be 0 are active low and are not driven during bus hold . the AM486DX4 processor provides four special bus c y - cles to indicate that certain instructions have been e x - ecuted, or certain conditions have occurred internally. the special bus cycles (in table 1) are defined when the bus cycle definition pins are in the following state: m / i o =0, d / c =0, and w / r =1. during these cycles the address bus is driven low while the data bus is undefine d . the external hardware must acknowledge these special bus cycles by returning rd y and brd y . ?????????????????????????????????????????????????????????????? ????????????????????????????????????????????????????????????? ? bs 8 / bs1 6 bus size 8 (active low; input)/ bus size 16 (active low; input ) these pins cause the AM486DX4 microprocessor to run multiple bus cycles to complete a request from devices that cannot provide or accept 32 bits of data in a single cycle. the bus sizing pins are sampled every clock. the state of these pins in the clock before rd y is used by the AM486DX4 microprocessor to determine the bus size. these signals are active low and are provided with internal pul l -up resistors. these inputs must satisfy se t - up and hold times, t 1 4 and t 1 5 , for proper operation . blas t burst last (active low; output ) blas t indicates that the next time brd y is returned, then the burst bus cycle is complete. blas t is active for both burst and no n -burst bus cycles . blas t is active low and is not driven during bus hold . bof f backoff (active low; input ) this input pin forces the AM486DX4 microprocessor to float its bus in the next clock. the microprocessor floats all pins normally floated during bus hold, but hlda is not asserted in response to bof f . bof f has higher priority than rd y or brd y ; if both are returned in the same clock, bof f takes effect. the microprocessor r e - mains in bus hold until bof f is negated. if a bus cycle is in progress when bof f is asserted, the cycle is r e - started. bof f is active low and must meet setup and hold times, t 18 a and t 1 9 , for proper operation . table 1 . special bus cycle encodin g be 3 be 2 be 1 be 0 special bus cycle s 1 1 1 0 shutdow n 1 1 0 1 flus h 1 0 1 1 hal t 0 1 1 1 write bac k
amd AM486DX4 microprocessor 9 p r e l i m i n a r y brd y burst ready input (active low; input ) this input pin performs the same cycle during a burst cycle that rd y performs during a no n -burst cycle. brdy indicates that the external system has presented valid data in response to a read or that the external system has accepted data in response to write. brd y is ignored when the bus is idle and at the end of the first clock in a bus cycle. brd y is sampled in the second and su b - sequent clocks of a burst cycle. the data presented on the data bus is strobed into the microprocessor when brd y is sampled active. if rd y is returned simult a - neously with brd y , brd y is ignored and the burst cycle is prematurely aborted. brd y is active low and is pr o - vided with a small pul l -up resistor. brd y must satisfy the setup and hold times, t 1 6 and t 1 7 . bre q internal cycle pending (active high; output ) breq indicates that the AM486DX4 microprocessor has internally generated a bus request. breq is ge n - erated whether or not the AM486DX4 microprocessor is driving the bus. breq is active high and is never floated, except for thre e -state test mode (see flus h ) . cl k clock (input ) clk is a 1x clock providing the fundamental timing for the bus interface unit and is multiplied in accordance with the clkmul pin to provide the internal frequency for the AM486DX4 microprocessor. all external timing parameters are specified with respect to the rising edge of clk . clkmu l clock multiplier (input ) the clock multiplier input defines the ratio of internal core clock frequency to external bus frequency. if sa m - pled low, the core frequency operates at twice the e x - ternal bus frequency (speed-double mode). if driven high or left floating speed-triple mode is selected. cl k - mul has an internal pull-up to v c c and may be left floa t - ing in designs that wish to select speed-triple clock mode . d31?d 0 data lines (inputs/outputs ) lines d7?d0 define the least significant byte and lines d31?d24 define the most significant byte. these si g - nals must meet setup and hold times t 2 2 and t 2 3 for pro p - er operation on reads. the pins are driven during the second and subsequent write cycle clocks . d / c , m / i o , w / r data/control, memory/input/output, write/rea d (active high/active low; output ) these are the primary bus definition signals (in table 2). these signal are driven valid as the ad s signal is asserted. the bus definition signals are not driven du r - ing bus hold and follow the timing of the address bus . the d / c bus cycle definition pin distinguishes memory and i/o data cycles (d) from the control cycles (c): i n - terrupt acknowledge, halt, and instruction fetching . the m / i o bus cycle definition pin distinguishes memory cycles (m) from input/output cycles ( i o ) . the w / r bus definition pin distinguishes write cycles from read cycles . ????????????????????????????????????????????????????????????? ? table 2. bus cycle definitio n ????????????????????????????????????????????????????????????? ? dp3?dp 0 data parity (active high; inputs/outputs ) data parity is generated on all write data cycles using the same timing as the data lines. even parity inform a - tion must be driven back into the microprocessor on the data parity pins with the same timing as read inform a - tion. this process ensures that the correct parity check status is indicated. the signals read on these pins do not affect program execution. input signals must meet setup and hold times, t 2 2 and t 2 3 . dp3?dp0 should be connected to v c c through a pul l -up resistor in systems not using parity. dp3?dp0 are active high and are dri v - en during the second and subsequent clocks of write cycles . ead s valid external address (active low; input ) this pin indicates a valid external address has been driven onto the AM486DX4 microprocessor address pins. this address is used to perform an internal cache invalidation cycle. ead s is active low and is provided with an internal pul l -up resistor. ead s must satisfy set- up and hold times, t 1 2 and t 1 3 , for proper operation . fer r floatin g -point error (active low; output ) driven active when a floatin g -point error occurs. ferr is similar to the erro r pin on a 387 math coprocessor. m / i o d / c w / r bus cycle initiate d 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 interrupt acknowledge halt/special cycle i/o read i/o write code read reserved memory read memory writ e
amd 1 0 AM486DX4 microprocessor p r e l i m i n a r y fer r is included for compatibility with systems using do s -type floatin g -point error reporting. fer r is active low, and is not floated during bus hold, except during thre e -state test mode (see flus h ) . flus h cache flush (active low; input ) flus h forces the AM486DX4 microprocessor to flush its entire internal cache. flus h is active low and need only be asserted for one clock. flus h is asynchronous but setup and hold times, t 2 0 and t 2 1 , must be met for recognition in any specific clock. flus h being sampled low in the clock before the falling edge of reset cau s - es the AM486DX4 microprocessor to enter the thre e -state test mode . hld a hold acknowledge (active high; output ) hlda goes active in response to a hold request pr e - sented on the hold pin. hlda indicates that the AM486DX4 microprocessor has given the bus to anot h - er local bus master. hlda is driven active in the same clock that the AM486DX4 microprocessor floats its bus. hlda is driven inactive when leaving bus hold. hlda is active high and remains driven during bus hold. hlda is never floated except during thre e -state test mode (see flus h ). hol d bus hold request (active high; input ) this input pin allows another bus master complete co n - trol of the AM486DX4 microprocessor bus. in response to hold going active, the AM486DX4 microprocessor floats most of its output and input/output pins. hlda is asserted after completing the current bus cycle, burst cycle, or sequence of locked cycles. the AM486DX4 microprocessor remains in this state until hold is dea s - serted. hold is active high and is not provided with an internal pul l -down resistor. hold mus t satisfy setup and hold times t 18 and t 1 9 for proper operation . ignn e ignore numeric error (active low; input ) when this pin is asserted, the AM486DX4 microproce s - sor will ignore a numeric error and continue executing no n -control floatin g -point instructions. when ignn e is deasserted, the AM486DX4 microprocessor will freeze on a no n -control floatin g -point instruction if a previous floatin g -point instruction caused an error. ignn e has no effect when the ne bit in control register 0 is set. ignn e is active low and is provided with a small inte r - nal pul l -up resistor. ignn e is asynchronous but must meet setup and hold times, t 2 0 and t 2 1 , to ensure reco g - nition in any specific clock . int r maskable interrupt (active high; input ) intr indicates an external interrupt has been genera t - ed. if the internal interrupt flag is set in eflags, active interrupt processing is initiated. the AM486DX4 micr o - processor generates two locked interrupt acknowledge bus cycles in response to the intr pin going active. intr must remain active until the interrupt acknowled g - es have been performed. this ensures that the interrupt is recognized. intr is active high and is not provided with an internal pul l -down resistor. intr is asynchr o - nous, but must meet setup and hold times, t 2 0 and t 2 1 , for recognition in any specific clock . ke n cache enable (active low; input ) ke n is used to determine whether the current cycle is cacheable. when the AM486DX4 microprocessor ge n - erates a cacheable cycle and ke n is active, the cycle becomes a cache line fill cycle. returning ke n active one clock before rd y during the last read in the cache line fill causes the line to be placed in the o n -chip cache. ke n is active low and is provided with a small internal pul l -up resistor. ke n must satisfy setup and hold times, t 14 and t 1 5 , for proper operation. loc k bus lock (active low; output ) loc k indicates the current bus cycle is locked. the AM486DX4 microprocessor does not allow a bus hold when loc k is asserted (but address holds are a l - lowed). loc k goes active in the first clock of the first locked bus cycle and goes inactive after the last clock of the last locked bus cycle. the last locked cycle ends when rd y is returned. loc k is active low and is not driven during bus hold. locked read cycles are not tran s - formed into cache fill cycles if ke n is active . nm i no n -maskable interrupt (active high; input) a high nmi signal indicates that external no n -maskable interrupt occurred. nmi is rising edge sensitive, but must be held low for at least four-clk periods before the rising edge. nmi does not have an internal pul l -down resistor. nmi is asynchronous, but must meet setup and hold times, t 2 0 and t 2 1 , for recognition in any specific clock . pcd/pw t page cache disable/page writ e -through (active high; outputs ) the outputs reflect the state of the page attribute bits, pwt and pcd, in the page table or page directory entry. if paging is disabled or unpaged cycles occur, pwt and pcd reflect the state of the pwt and pcd bits in control register 3. pwt and pcd have the same timing as the cycle definition pins (m / i o , d / c , and w / r ). pwt and pcd are active high and are not driven during bus hold. pcd is masked by the cache disable bit (cd) in control register 0.
amd AM486DX4 microprocessor 11 p r e l i m i n a r y pch k parity status (active low; output ) parity status is driven on the pch k pin the clock after rd y for read operations for data sampled at the end of the previous clock. a parity error is indicated by pchk being low. parity status is only checked for enabled bytes as indicated by the byte enable and bus size si g - nals. pch k is valid only in the clock immediately after read data is returned to the microprocessor. at all other times pch k is inactive high. pch k is never floated e x - cept during thre e -state test mode (see flus h ) . ploc k pseud o -lock (active low; output ) ploc k indicates that the current bus transaction r e - quires more than one bus cycle to complete. examples of such operations are floatin g -point long reads and writes (64 bits), segment table descriptor reads (64 bits), and cache line fills (128 bits). the AM486DX4 micr o - processor drives ploc k active until the addresses for the last bus cycle of the transaction have been driven, regardless of whether rd y or brd y has been returned. normally ploc k and blas t are inverse of each other. however, during the first bus cycle of a 6 4 -bit floatin g - point write, both ploc k and blas t will be asserted. ploc k is a function of the bs 8 , bs1 6 , and ke n inputs. ploc k should be sampled only if the clock rd y is r e - turned. ploc k is active low and is not driven during bus hold . rese t reset (active high; input ) this pin forces the AM486DX4 microprocessor to begin execution at a known state. the microprocessor cannot begin execution of instructions until at least 1 ms after v cc and clk have reached their proper dc and ac specifications. the reset pin should remain active during this time to ensure proper microprocessor ope r - ation. reset is active high. reset is asynchronous but must meet setup and hold times, t 2 0 and t 2 1 , for re c - ognition in any specific clock. rd y no n -burst ready (active low; input ) this input pin indicates that the current bus cycle is co m - plete. rd y indicates that the external system has pr e - sented valid data on the data pins in response to a read, or that the external system has accepted data from the AM486DX4 microprocessor in response to a write. rdy is ignored when the bus is idle and at the end of the bus cycle?s first clock . rd y is active during address hold. data can be returned to the processor while ahold is active . rd y is active low and is not provided with an internal pul l -up resistor. rd y must satisfy setup and hold times, t 16 and t 1 7 , for proper chip operation . tc k test clock (input ) test clock is an input to the AM486DX4 cpu and pr o - vides the clocking function required by the jtag boun d - ary scan feature. tck is used to clock state information and data into and out of the component. state select information and data are clocked into the component on the rising edge of tck on tms and tdi, respectively. data is clocked out of the component on the falling edge of tck on tdo . td i test data input (input ) tdi is the serial input used to shift jtag instructions and data into the component. tdi is sampled on the rising edge of tck, during the shif t -ir and the shif t -dr tap controller states. during all other tap controller states, tdi is a ?don?t care. ? td o test data output (output ) tdo is the serial output used to shift jtag instructions and data out of the component. tdo is driven on the falling edge of tck during the shif t -ir and shif t -dr test access port (tap) controller states. at all other times, tdo is driven to the high-impedance state . tm s test mode select (input ) tms is decoded by the jtag tap to select the operation of the test logic. tms is sampled on the rising edge of tck. to guarantee deterministic behavior of the tap controller, tms is provided with an internal pul l -up r e - sistor . u p upgrade present (active low; input ) the upgrade present pin forces the AM486DX4 cpu to thre e -state all its outputs and enter the powe r -down mode. when the upgrade present pin is sampled a s - serted by the cpu in the clock before the falling edge of reset, the powe r -down mode is enabled. u p has no effect on the powe r -down status except during this edge. the cpu is also forced to thre e -state all of its outputs immediately in response to this signal. the up signal must remain asserted in order to keep the pins thre e -state. u p is active low and is provided with an internal pul l -up resistor . volde t voltage detect (active low; output ) the voltage detect signal allows external system logic to distinguish between a 5-v am486 processor and the 3.3-v AM486DX4 processor. the signal is active low for a 3.3-v AM486DX4 processor .
amd 1 2 AM486DX4 microprocessor p r e l i m i n a r y table 3. output pin s nam e active leve l floated a t breq hlda be 3 ? be0 pcd/pwt w / r , d / c , m / io lock plock ads blast pchk a3?a2 fer r volde t high high low high high low low low low low high lo w lo w three-state test mode three-state test mod e bus hold bus hold bus hold bus hold bus hold bus hold bus hol d three-state test mode bus, address hol d three-state test mode - table 4. input pin s nam e active leve l synchronous/ asynchronou s clk reset hold ahold eads boff flush a20m bs1 6 , bs8 ken rdy brdy intr nmi up ignne clkmu l - high high high low low low low low low low low high high low low - - asynchronous synchronous synchronous synchronous synchronous asynchronous asynchronous synchronous synchronous synchronous synchronous asynchronous asynchronous asynchronous asynchronous - table 5. input/output pin s nam e active leve l floated a t d31??d0 dp3?dp0 a31?a 4 high high hig h bus hold bus hold bus, address hol d table 6. test pin s nam e input or outpu t sampled/driven o n tck tdi tdo tm s input input output inpu t n/a rising edge of tck falling edge of tck rising edge of tc k
amd AM486DX4 microprocessor 13 p r e l i m i n a r y cpu identification code s the dx register always contains a component identif i - cation at the conclusion of reset. the upper byte of dx (dh) contains 04 and the lower byte of dx (dl) contains a cpu type/stepping identifier . architectural overvie w the AM486DX4 processor is a 3 2 -bit architecture with o n -chip memory management and cache memory units. it is a fully compatible member of the am486 fa m - ily . o n -chip cache memory allows frequently used data and code to be stored o n -chip, thereby reducing accesses to the external bus. a clock multiplier has been added to speed up internal operations. risc design tec h - niques are used to reduce instruction cycle times. a burst bus feature enables fast cache fills. the am486 cpu memory management unit (mmu) consists of a segmentation unit and a paging unit. se g - mentation allows management of the logical address space by providing easy data and code relocatibility and efficient sharing of global resources. the paging mec h - anism operates beneath segmentation and is transpa r - ent to the segmentation process. paging is optional and can be disabled by system software. each segment can be divided into one or more 4 -kbyte segments. to i m - plement a virtual memory system, the AM486DX4 m i - croprocessor supports full restartability for all page and segment faults . memory is organized into one or more variable length segments, each up to 4 gbyte ( 2 3 2 bytes) in size. a segment can have attributes associated with it. these table 7. cpu i d component id (dh ) component id (dl ) 0 4 3 2 table 8. jtag id cod e version cod e part number cod e manufacturer identit y 00 h 043 2 0 1 attributes include its location, size, type (i.e., stack, code, or data), and protection characteristics. each task on an AM486DX4 microprocessor can have a maximum of 16,381 segments, each up to 4 gbyte in size. thus, each task has a maximum of 64 tbyte (terabytes) of virtual memory . the segmentation unit provides four levels of protection for isolating and protecting applications and the opera t - ing system from each other. the hardware enforced pr o - tection allows high integrity system designs . the AM486DX4 microprocessor has three modes of o p - eration: real address mode (real mode), virtual a d - dress mode (protected mode), and within protected mode, tasks may be performed in virtual 8086 mod e . in real mode, the AM486DX4 microprocessor operates as a very fast 8086. real mode is required primarily to set up the processor for protected mode operation. pr o - tected mode provides access to the sophisticated me m - ory management paging and privilege capabilities of the processor . within protected mode, software can perform a task switch to enter into tasks designated as virtual 8086 mode tasks. each virtual 8086 task behaves with 8086 semantics, allowing 8086 software (an application pr o - gram or an entire operating system) to execute . the o n -chip cache is 8 kbyte. it is fou r -way set associ a - tive and follows a writ e -through policy. the o n -chip cache includes features that provide flexibility in exte r - nal memory system design. individual pages can be designated as cacheable or no n -cacheable by software or hardware. the cache can also be enabled and di s - abled by software or hardware . finally, the AM486DX4 microprocessor has features that facilitate hig h -performance hardware designs. the clock multiplier improves execution performance wit h - out increasing the board design complexity. this clock multiplier enhances all operations operating out of the cache and/or not blocked by external bus assesses. the burst bus feature enables fast cache fills .
amd AM486DX4 microprocessor 14 p r e l i m i n a r y electrical dat a the following sections describe recommended electr i - cal connections for the AM486DX4 microprocessor and its electrical specifications . power and groundin g power connection s the AM486DX4 cpu is implemented in 0.5 micron cmos 3-layer metal technology and has modest power requirements. however, its high clock frequency output buffers can cause power surges as multiple output buf f - ers drive new signal levels simultaneously. for clean, o n -chip power distribution at high frequency, 23 v c c and 28 v s s pins feed the AM486DX4 microprocessor . power and ground connections must be made to all e x - ternal v c c and gnd pins of the AM486DX4 micropr o - cessor. on the circuit board, all v c c pins must be connected on a v c c plane. all v s s pins must likewise be connected on a gnd plane . power decoupling recommendations liberal decoupling capacitance should be placed near the AM486DX4 microprocessor. the AM486DX4 m i - croprocessor, driving its 3 2 -bit parallel address and data buses at high frequencies, can cause transient power surges, particularly when driving large capac i - tive loads . low inductance capacitors and interconnects are re c - ommended for best hig h -frequency electrical perfo r - mance. inductance can be reduced by shortening ci r - cuit board traces between the AM486DX4 cpu, and decoupling capacitors as much as possible. capacitors specifically for pga packages are also commercially available . system clock recommendation s the clk input to the AM486DX4 processor should not be driven until v c c has reached its normal operating level (3.3 v). once v c c has reached its normal operating level, the AM486DX4 cpu can handle the clock fr e - quency for which it is specified and the oscillator/clock driver should have locked onto its desired frequency . other connection recommendation s nc pins should always remain unconnected . for reliable operation, always connect unused inputs to an appropriate signal level. active low inputs should be connected to v c c through a pul l -up resistor. pul l -ups in the range of 20 k w are recommended. active high inputs should be connected to gnd . inc is electrically isolated and has no special requir e - ments .
amd AM486DX4 microprocessor 15 p r e l i m i n a r y absolute maximum ratings case temperature under bias .......... ? 6 5 c to +11 0 c storage temperature ........................ ? 6 5 c to +15 0 c voltage on any pin with respect to ground ............ ?0.5 v to v c c +2.6 v supply voltage with respect to v s s ................................ ?0.5 v to +4.6 v stresses above those listed under absolute maximum ra t - ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute ma x - imum ratings for extended periods may affect device reliability . operating range s commercial (c) device s t cas e ....................................................... 0 c to +8 5 c v c c .......................................................... 3.3 v 0.3 v operating ranges define those limits between which the fun c - tionality of the device is guaranteed . dc characteristics over commercial operating range s functional operating range: v c c = 3.3 v 0.3 v; t cas e = 0 c to +8 5 c . notes : 1. this parameter is measured at: address, data, be 3 ? be 0 4.0 ma definition, control 5.0 m a 2. this parameter is measured at: address, data, be 3 ? be 0 ?1.0 ma definition, control ?0.9 m a 3. typical supply current: 800 ma @ 100 mhz or 960 ma @ 120 mh z 4. this parameter is for inputs without pul l -ups or pul l -downs and 0 v in v c c . 5. this parameter is for inputs with pul l -downs and v i h =2.4 v . 6. this parameter is for inputs with pul l -ups and v i l =0.45 v . 7. not 100% tested . 8. this parameter is for inputs without pull-ups or pull-downs and v c c v i n 5v . 9. this parameter is for three-state outputs where v ex t is driven on the three-state output and 0 v ex t v c c . 10. this parameter is for three-state outputs where v ex t is driven on the three-state output and v c c v ex t 5v . symbo l parameter descriptio n note s preliminar y uni t mi n ma x v i l input low voltag e ? 0. 3 + 0. 8 v v i h input high voltag e 2. 0 v c c +2. 4 v v o l output low voltag e i o l =(note 1 ) 0.4 5 v v o h output high voltag e i o h =(note 2 ) 2. 4 v i c c power supply curren t 100 mhz (note 3) 120 mhz (note 3 ) 1000 120 0 m a i l i input leakage curren t (note 4 ) (note 8 ) 1 5 5 0 m a i i h input leakage curren t (note 5 ) 20 0 m a i i l input leakage curren t (note 6 ) ? 40 0 m a i l o output leakage curren t (note 9 ) (note 10 ) 1 5 5 0 m a c in input capacitance f c =1 mhz (note 7 ) 1 0 p f c out i/o or output capacitanc e f c =1 mhz (note 7 ) 1 4 p f c clk clk capacitanc e f c =1 mhz (note 7 ) 1 2 p f
amd 1 6 AM486DX4 microprocessor p r e l i m i n a r y switching characteristic s the switching characteristics consist of output delays, input setup requirements, and input hold requirements. all switching characteristics are relative to the rising edge of the clk signal . the switching characteristics measurements are d e - fined by figures 2 - 9. inputs must be driven to the vol t - age levels indicated by figure 2 when switching cha r - acteristics ar e measured . AM486DX4 microprocessor output delays are specified with minimum and maximum limits. the minimum AM486DX4 microprocessor delay times are hold times provided to external circuitry. AM486DX4 microprocessor input setup and hold times are specified as minimums, defining the smallest acceptable sampling windows. within the sampling windows, a synchronous input signal must be stable for correct AM486DX4 microprocessor operation .
1 7 AM486DX4 microprocessor amd p r e l i m i n a r y switching characteristics over commercial operating range s operating frequency/bus frequency: 120/40mh z ; t cas e = 0 c to +8 5 c; c l =50 pf unless otherwise specified . not e : 1.not 100% tested. guaranteed by design characterization . preliminar y symbo l parameter descriptio n note s figur e mi n ma x uni t operating frequenc y 8 4 0 mh z t 1 clk perio d 2 2 5 12 5 n s t 1 a clk period stabilit y adjacent clock s 0.1 % d t 2 clk high tim e @ 2.0 v 2 9 n s t 3 clk low tim e @ 0.8 v 2 9 n s t 4 clk fall tim e 2 3 n s t 5 clk rise tim e 2 3 n s t 6 a3 1 - a2, pwt, pcd, m / i o , be 3 - be 0 , d / c , w / r , ad s , loc k , fer r , breq, hlda valid dela y 7 3 1 4 n s t 7 a3 1 - a2, pwt, pcd, m / i o , be 3 - be 0 , d / c , w / r , ad s , loc k , fer r , breq, hld a float dela y (note 1 ) 8 3 1 8 n s t 8 pch k valid dela y 6 3 1 6 n s t 8 a blas t , ploc k valid dela y 7 3 1 8 n s t 9 blas t , ploc k float dela y (note 1 ) 8 3 1 6 n s t 1 0 d3 1 - d0, dp 3 - dp0 write data valid dela y 7 3 1 6 n s t 1 1 d3 1 - d0, dp 3 - dp0 write data float dela y (note 1 ) 8 3 1 8 n s t 1 2 ead s setup tim e 4 5 n s t 1 3 ead s hold tim e 4 3 n s t 1 4 ke n , bs1 6 , bs 8 setup tim e 4 5 n s t 1 5 ke n , bs1 6 , bs 8 hold tim e 4 3 n s t 1 6 rd y , brd y setup tim e 5 5 n s t 1 7 rd y , brd y hold tim e 5 3 n s t 1 8 hold, ahold setup tim e 4 6 n s t 18 a bof f setup tim e 4 8 n s t 1 9 hold, ahold, bof f hold tim e 4 3 n s t 2 0 reset, flus h , a20 m , nmi, intr , ignn e setup time 3, 4 5 n s t 2 1 reset, flus h , a20 m , nmi, int r , ignn e hold tim e 3, 4 3 n s t 2 2 d3 1 - d0, dp 3 - dp0, a3 1 - a4 read setup time 4, 5 5 n s t 2 3 d3 1 - d0, dp 3 - dp0, a3 1 - a4 read hold tim e 4, 5 3 n s
amd 1 8 AM486DX4 microprocessor p r e l i m i n a r y operating frequency/bus frequency: 100/33 mh z ; t cas e = 0 c to +8 5 c; c l =50 pf unless otherwise specified . not e : 1.not 100% tested. guaranteed by design characterization . preliminar y symbo l parameter descriptio n note s figur e mi n ma x uni t operating frequenc y 8 3 3 mh z t 1 clk perio d 2 3 0 125. 5 n s t 1 a clk period stabilit y adjacent clock s 0.1 % d t 2 clk high tim e @ 2.0 v 2 1 1 n s t 3 clk low tim e @ 0.8 v 2 1 1 n s t 4 clk fall tim e 2 3 n s t 5 clk rise tim e 2 3 n s t 6 a31?a2, pwt, pcd, m / i o , be 3 ? be 0 , d / c , w / r , ad s , loc k , fer r , breq, hlda valid dela y 7 3 1 4 n s t 7 a31?a2, pwt, pcd, m / i o , be 3 ? be 0 , d / c , w / r , ad s , loc k , fer r , breq, hlda float dela y (note 1 ) 8 2 0 n s t 8 pch k valid dela y 6 3 1 4 n s t 8 a blas t , ploc k valid dela y 7 3 1 4 n s t 9 blas t , ploc k float dela y (note 1 ) 8 2 0 n s t 1 0 d31?d0, dp3?dp0 write data valid dela y 7 3 1 4 n s t 1 1 d31?d0, dp3?dp0 write data float dela y (note 1 ) 8 2 0 n s t 1 2 ead s setup tim e 4 5 n s t 1 3 ead s hold tim e 4 3 n s t 1 4 ke n , bs1 6 , bs 8 setup tim e 4 5 n s t 1 5 ke n , bs1 6 , bs 8 hold tim e 4 3 n s t 1 6 rd y , brd y setup tim e 5 5 n s t 1 7 rd y , brd y hold tim e 5 3 n s t 1 8 hold, ahold setup tim e 4 6 n s t 18 a bof f setup tim e 4 7 n s t 1 9 hold, ahold, bof f hold tim e 4 3 n s t 2 0 reset, flus h , a20 m , nmi, intr, ignne setup time 3, 4 5 n s t 2 1 reset , flus h , a20 m , nmi, intr, ignne hold tim e 3, 4 3 n s t 2 2 d31?d0, dp3?dp0, a31?a4 read setup time 4, 5 5 n s t 2 3 d31?d0, dp3?dp0, a31?a4 read hold tim e 4, 5 3 n s
1 9 AM486DX4 microprocessor amd p r e l i m i n a r y AM486DX4 cpu ac characteristics for boundary scan test signals at 25 mh z v c c = 3.3 v 0.3 v; t cas e = 0 c to +8 5 c; c l = 50 pf. all inputs and outputs are ttl level. notes : 1. rise/fall times are measured between 0.8 v and 2.0 v. rise/fall times can be relaxed by 1 ns per 1 0 -ns increase in tck period . 2. tck period > clk period . 3. parameter measured from tck . symbo l parameter mi n ma x uni t figur e note s t 2 4 tck frequenc y 2 5 mh z 1x cloc k t 2 5 tck perio d 4 0 n s 9 note 2 t 2 6 tck high tim e 1 0 n s at 2.0 v t 2 7 tck low tim e 1 0 n s at 0.8 v t 2 8 tck rise tim e 4 n s note 1 t 2 9 tck fall tim e 4 n s note 1 t 3 0 tdi, tms setup tim e 8 n s 9 note 3 t 3 1 tdi, tms hold tim e 7 n s 9 note 3 t 3 2 tdo valid dela y 3 2 5 n s 9 note 3 t 3 3 tdo float dela y 3 0 n s 9 note 3 t 3 4 all outputs (no n -test) valid dela y 3 2 5 n s 9 note 3 t 3 5 all outputs (no n -test) float dela y 3 6 n s 9 note 3 t 3 6 all inputs (no n -test) setup tim e 8 n s 9 note 3 t 3 7 all inputs (no n -test) hold tim e 7 n s 9 note 3
amd 2 0 AM486DX4 microprocessor p r e l i m i n a r y ks00000 must be stead y may change from h to l may change from l to h does not appl y don?t care, any change permitte d will be stead y will be changing from h to l will be changing from l to h changing, state unknow n center line is hig h - impedance ?off? stat e wavefor m input s output s figure 1. change state diagra m t 5 2.0 v 1.5 v 0.8 v figure 2. clk waveform s 17852b-095 t 2 t 3 t 4 t 1
2 1 AM486DX4 microprocessor amd p r e l i m i n a r y t x t x t x clk reset t 2 0 t x t 2 1 rese t initialization sequenc e figure 3. reset setup and hold timin g 19160c.00 3 clk eads bs 8 , bs1 6 , ken t x t x t x t x bof f , ahold, hold rese t , flus h , a20 m , ignn e , intr, nmi a31?a4 (read) figure 4. input setup and hold timin g 19160c.004 t 1 2 t 1 3 t 1 5 t 1 4 t 18 a t 1 9 t 2 1 t 2 2 t 2 3 t 2 0
amd 2 2 AM486DX4 microprocessor p r e l i m i n a r y rd y , brdy d31?d0 dp3?dp0 (read) 1.5 v 1.5 v figure 5. rd y and brd y input setup and hold timin g 19160c.005 t 1 6 t 2 2 t 1 7 t 2 3 clk t 2 t x t x t x clk brd y , rdy pchk t 2 t x t x t x valid min max figure 6. pch k valid delay timin g 19160c.006 d31?d0 dp3?dp0 (read) t 8 valid clk a31?a2, pwt, pcd, be 3 ? be 0 , m / i o , d / c , w / r , ad s , loc k , fer r , breq, hlda blas t , plock t x t x t x d31?d0, dp3?dp0, (write) min max t x valid n +1 min max valid n +1 valid n min max valid n +1 19160c.007 figure 7. output valid delay timin g t 6 t 1 0 t 8 a valid n valid n
2 3 AM486DX4 microprocessor amd p r e l i m i n a r y clk a3 1 - a2, pwt, pcd, be 3 - be 0 , m / i o , d / c , w / r , ad s , loc k , fer r , breq, hlda blas t , plock t x t x t x d3 1 - d0, dp 3 - dp0 (write) valid t x valid valid figure 8. maximum float delay timin g 17852a-103 t 6 t 1 0 t 8 a min min min t 7 t 1 1 t 9 tck tdi, tms tdo output signals input signals figure 9. test signal timing diagra m 17852b-104 t 2 5 t 3 0 t 3 1 t 3 2 t 3 4 t 3 5 t 3 6 t 3 7 t 3 3
amd 2 4 AM486DX4 microprocessor p r e l i m i n a r y package thermal specification s the AM486DX4 microprocessor is specified for oper a - tion when t cas e (the case temperature) is within the range of 0 c to +8 5 c. t cas e can be measured in any environment to determine whether the AM486DX4 m i - croprocessor is within specified operating range. the case temperature should be measured at the center of the top surface opposite the pins . the ambient temperature ( t a ) is guaranteed as long as t cas e is not violated. the ambient temperature can be calculated from q j c and q j a and from the following equations : t j = t case + p ? q j c t a = t j ? p ? q j a t cas e = t a + p ? [ q j a ? q j c ] where : t j , t a , t cas e = junction, ambient, and case temper a - ture . q j c , q j a = junctio n -t o -case and junctio n -t o -ambient thermal resistance, respectively . p = maximum power consumptio n the values for q j a and q j c are given in table 9 for the 1.75 sq. in., 16 8 -pin, ceramic pga . table 10 shows the t a allowable (without exceeding t cas e ) at various airflows and operating frequencies (clock). note that t a is greatly improved by attaching fins or a heat sink to the package. heat sink dime n - sions are shown in figure 10. p (the maximum power consumption) is calculated by using the maximum i cc at 3.3 v as tabulated in the dc characteristic s . ????????????????????????????????????????????????????????????? ? *0.35 0 2 high unidirectional heat sink (al alloy 6063-t5, 40 mil fin width, 155 mil cente r -t o -center fin spacing) . table 9. thermal resistance (c/w) q j c and q j a for the 168-pin, ceramic pga packag e q j c q j a vs. airflow-ft/min. (m/sec ) 0 (0 ) 200 (1.01 ) 400 (2.03) 600 (3.04 ) 800 (4.06 ) 1000 (5.07 ) no heat sin k 1. 5 16. 5 14. 0 12. 0 10. 5 9. 5 9. 0 heat sink * 2. 0 12. 0 7. 0 5. 0 4. 0 3. 5 3.2 5 heat sink* and fa n 2. 0 5. 0 4. 6 4. 2 3. 8 3. 5 3.2 5 table 10. maximum t a at various airflows in c cloc k airflow-ft/min. (m/sec ) 0 (0 ) 200 (1.01 ) 400 (2.03 ) 600 (3.04 ) 800 (4.06 ) 1000 (5.07 ) t a ?no heat sin k 100 mh z 31. 0 41. 8 49. 0 54. 4 58. 0 59. 8 t a ?heat sin k 100 mh z 49. 0 67. 0 74. 2 77. 8 79. 6 80. 5 120 mh z 41. 8 63. 4 72. 0 76. 4 78. 5 79. 6 t a ?heat sink and fa n 100 mh z 74. 2 75. 6 77. 1 78. 5 79. 6 80. 5 120 mh z 72. 0 73. 8 75. 5 77. 2 78. 5 79. 6 figure 10. heat sink dimensions 0.29 0 2 0.10 0 2 0.04 0 2 1.5 3 2 0.35 0 2 0.06 0 2 0.11 5 2 17852b-113
2 5 AM486DX4 microprocessor amd p r e l i m i n a r y physical dimension s for reference only. all dimensions are measured in inches. bsc is an ansi standard for basic space centering . 1.735 1.765 1.735 1.765 bottom view (pins facing up) base plane seating plane 0.140 0.180 0.110 0.140 0.105 0.125 0.017 0.020 side view cgm 168 16734c 5/11/93 mh 0.025 0.045 1.595 1.605 1.595 1.605 index corner 0.090 0.110 amd, am386, and am486 are registered trademarks of advanced micro devices, inc. fusionpc is a service mark of advanced micro devices, inc. microsoft and windows are registered trademarks of microsoft corp . product names used in this publication are for identification purposes only and may be trademarks of their respective companies .
amd 2 6 AM486DX4 microprocessor p r e l i m i n a r y

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